Semiconductor storage devices having a split-gate non-volatile memory include those having a memory cell in which a pair of impurity regions 102a, 102b are formed in the main surface of a substrate 101 with a channel region interposed between them, a select gate electrode 104 is formed on the channel region via a gate insulating film 103, and sidewall-shaped control gate electrodes 106a, 106b are formed on both side faces of the select gate electrode 104 and on the surface of the channel region (the channel region in the area between the impurity regions 102a, 102b and select gate electrode 104) via a gate-isolation insulating film 105 (e.g., ONO film) (see FIGS. 6, 7, 9 and 10, for example, see Patent Documents 1 and 2). If this cell is selected by supplying the select gate electrode 104 with a prescribed potential in this semiconductor storage device, controlling the potential supplied to the impurity regions 102a, 102b and control gate electrodes 106a, 106b enables electric charge to be stored in and written to the gate-isolation insulating film 105 underlying the control gate electrodes 106a, 106b, to be read out and to be expelled and erased from the gate-isolation insulating film 105.
As illustrated in FIG. 8, a circuit in which such memory cells are arrayed is such that one impurity region of the cell is connected to a bit line driver (not shown) via a bit line (BL1, BL2, BL3, BL4), the other impurity region of the memory cell is connected to ground (GND) via a common source line (CS), one control gate electrode of the memory cell (the control gate electrode on the side of that impurity region connected to the common source line) is connected to a control gate driver (not shown) via wiring (CG1, CG2), the other control gate electrode of the memory cell (the control gate electrode on the side of that impurity region connected to the bit line) is connected to ground via wiring, and the select gate electrode of the memory cell is connected to a word line driver (not shown) via a word line (WL1, WL2, WL3, WL4). The bit line (BL1, BL2, BL3, BL4) is connected to the one impurity region of each of the memory cells arrayed in the direction of the corresponding row and is connected to the common impurity regions of mutually adjacent memory cells. The common source line (CS) is connected to the other impurity region of each of the memory cells irrespective of the row and column directions and is connected to the common impurity regions of mutually adjacent memory cells. The word line (WL1, WL2) is connected to the select gate electrode of each of the memory cells arrayed in the column direction. The control gate electrodes placed on both sides of the impurity region connected to the common source line (CS) are at a common potential owing to control of the control gate driver (not shown). The control gate electrodes placed on both sides of the impurity region connected to the bit line (BL1, BL2, BL3, BL4) are at the common ground potential. For example, in order to select the selected cell enclosed by the dotted line in FIG. 8, the bit line BL2 and word line WL3 are selected by the bit line driver (not shown) and word line driver (not shown), respectively.
This semiconductor storage device is such that a semiconductor storage device similar to that shown in FIG. 7 is manufactured by forming the select gate electrode 104 on the channel region of substrate 101 via the gate insulating film 103 (see FIG. 9A); forming the gate-isolation insulating film 105 on the surface of substrate 101 inclusive of the select gate electrode 104 (see FIG. 9B); forming a silicon layer 106 on the surface of the gate-isolation insulating film 105 (see FIG. 9C); forming the sidewall-shaped control gate electrodes 106a, 106b by etching back (by anisotropic etching) the silicon layer 106 (see FIG. 10A); forming the pair of impurity regions 102a, 102b on both sides of the channel region of substrate 101 in self-aligning fashion (see FIG. 10B); and exposing the surfaces of the select gate electrode 104 and impurity regions 102a, 102b by removing the gate-isolation insulating film 105 on the select gate electrode 104 and impurity regions 102a, 102b (see FIG. 10C).
[Patent Document 1]
Japanese Patent Kokai Publication No. JP2002-231829A
[Patent Document 2]
Japanese Patent Kokai Publication No. JP2002-289711A